Suppose that Q1 = 0 and Q2 = 1 is the initial state of the two JK flip-flop
circuit shown. What is the state of the circuit after applying two complete
clock pulses?
2 is CORRECT. In this circuit, all the flip-flops (F/Fs) are connected to the same clock, and the J and K inputs of F/F#2 are connected to the Q and Q outputs of F/F#1; it resembles a synchronous counter circuit (the first two stages). Heres the analysis: F/F#1 toggles twice, once for each falling edge of the clock, since J = K = 1 always. Therefore after two toggles, Q1 will go 0 to 1 to 0. The same clock signals go to F/F#2, but notice that J and K for this flip flop are not always both 1. On the first falling edge, F/F #2 is reset, because Q1 was a 0 initially so that J = 0 and K = 1 for F/F#2. On the second falling edge, F/F#2 is set, because Q1 was a 1 earlier so that J = 1 and K = 0. [Draw a timing diagram to get full description:]
Initial state: Q1 = 0; Q2 = 1
CLK: _-_-_
Q1: __--_ Final state Q1: 0
Q2: --__- Q2: 1