5. Suppose that Q1 = 1 and Q2 = 0 is the initial state of the two JK flip-flop circuit shown. What is the state of the circuit after applying two complete clock pulses?

  1. Q1=0 Q2=0
  2. Q1=0 Q2=1
  3. Q1=1 Q2=0
  4. Q1=1 Q2=1



4 is CORRECT. In this problem only F/F#1 is connected to the clock; F/F#2 gets its clock from F/F#1 and both F/Fs are in the toggle mode. Thus this circuit resembles the first two stages of a ripple counter. F/F#1 toggles twice, once for each falling edge of the clock, since J = K = 1 always. Since Q1 = 1 initially, the final state of Q1 is 1. On the other hand, F/F#2 toggles once when Q1 makes a 1 to 0 transition, since its clock is driven by Q1. This circuit is not synchronous since F/F#2 is not tied to the common clock But we can draw a timing diagram anyway as: 

    Initial state: Q1 = 1; Q2 = 0  
    CLK: _-_-_ 
     Q1: --__-  Final state Q1: 1 
     Q2: __---              Q2: 1

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