(0011) | V (????) transient state #1 | V (????) transient state #2 | V (0100)
4 is CORRECT. 3 bits will change when the counter transits between count states QDQCQBQA = 0011 to 0100. Transient state #1 is entered when QA goes 1 to 0. Next, transient state #2 is entered when QB goes 1 to 0. Finally, count state 0100 is entered when QC goes 0 to 1. Note the ripple effect: QA changes, then QB changes, followed by QC. Here is the filled in state graph:
(0011) State 3 | V (0010) transient state #1 | V (0000) transient state #2 | V (0100) State 4