This exercise will examine the properties and applications of some important combinational logic circuits. Circuits to be considered include the decoder, multiplexer, encoder, demultiplexer as well as the ROM (read- only memory). (Go back to homepage.)

1. An 8-line to 1-line multiplexer is connected as shown, where output Y = F(x,y,z) and z is the least significant input. Which of the following functions does Y generate?
   1. F(x,y,z) = z
   2. F(x,y,z) = y
   3. F(x,y,z) = z'
   4. F(x,y,z) = x
   5. F(x,y,z) = x + y'
      
      
      
      
      
      
      
      

2. Which of the following is the correct output expression for an eight to one MUX?
   1. Y = D(m0 + m1 + m2 +...+ m7)
   2. Y = (D0*m0 + D1*m1 + D2*m2 +...+ D7*m7)*E
   3. Y = m0' + m1' + m2' +...+ m7'
   4. Y = (D0*m0' + D1*m1' + D2*m2' +...+ D7*m7')*E
   5. Y = D*m0 + D*m1 + D*m2 +...+ D*m7

3. A 3-line to 8-line decoder is connected as shown. Where x, y and z are inputs (z is the least significant input digit) and F is an output. Which of the following expressions correctly describes F?
   1. F(x,y,z) = z
   2. F(x,y,z) = x
   3. F(x,y,z) = z'
   4. F(x,y,z) = yz
   5. F(x,y,z) = x'
      
      
      
      
      

4. A circuit which gates one input of data line to one of 2^n output lines is defined as a
   1. MUX
   2. DeMUX
   3. Encoder
   4. Decoder
   5. ROM

5. A 3-line to 8-line decoder is connected as shown, where x, y, and z are inputs (z is the least significant input digit) and F is an output. F = 1 when
   1. All 3 inputs are logical 0
   2. 2 out of 3 inputs are logical 0
   3. 1 out of 3 inputs are logical 0
   4. No input is logical 0
   5. None of the above

6. A circuit which translates n input lines into an m-bit code word, where n <= 2^m is defined as a
   1. MUX
   2. DeMUX
   3. Encoder
   4. Decoder
   5. ROM

7. Which of the following correctly describes output Yi (i: 0 to 7) of the 3-line to 8-line decoder, where mi is the ith minterm of the CBA select lines and E is the enable input?
   1. Yi = mi*E
   2. Yi = (mi*E)'
   3. Yi = (mi*E')'
   4. Yi = (mi'*E)'
   5. Yi = (mi'*E')'
      
      
      
      
      

8. Which of the following occurs when the enable input to a 3-line to 8- line decoder goes low (i.e. E=0)? Assume outputs of the decoder are active-low.
   1. All outputs go low(0)
   2. All outputs go high(1)
   3. The outputs go to a random pattern of 0's and 1's
   4. Power to the decoder chip is lost
   5. None of the above

9. A ROM having 9 address lines and 16 outputs is given. What is the total capacity = C? Note: K = 1024 = 2^10
   1. 25K
   2. 13K
   3. 8K
   4. 9K
   5. 10K

10. A ROM having a total capacity of 64K bits (K = 1024 = 2^10) is given. If the ROM is known to have 8 outputs, how many address lines are there?
    1. 11
    2. 12
    3. 13
    4. 14
    5. 15

11. Read-Only Memories (ROM's) are constructed from which of the following components? Select the best answer.
    1. A DECODER and a MUX
    2. A MUX and a DEMUX
    3. A DECODER and an ENCODER
    4. A MUX and an ENCODER
    5. An ENCODER and a DEMUX

12. Which of the following best describes how to construct a 1-line to 8-line demultiplexer from a 3-line to 8-line decoder:
    1. Connect the decoder input select lines CBA to D.
    2. Connect the decoder enable input to D.
    3. Connect the decoder input data lines to Di.
    4. Connect the ith decoder output to Di.
    5. Connect Y to D and W to D'.