2. The logic circuit shown represents most closely the architecture of a

  1. Simple Latch
  2. SR Latch with Enable
  3. D Latch with Enable
  4. D Flip-Flop
  5. JK Flip-Flop



1 is WRONG. The latch is just the rightmost two cross coupled NAND gates. (Cross coupled means that the output of one gate feeds the inner input of the other gate.)

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